Present-day integrated circuit (IC) chips have advanced significantly in both complexity and sophistication. For example, in early generation chip designs, a chip might embody relatively simple electronic logic blocks effected by interconnections between logic gates; whereas, newer generation chips include designs having combinations of complex, modularized IC designs often called “cores”, which together constitute an entire SoC. These newer generation IC designs significantly increase the overall functionality and performance characteristics of the chip, itself, by for example, having the ability to include smaller feature sizes and thus increasing the amount of circuitry which can be built on a single chip. But, this comes at a cost: longer design and verification times which, in turn, translate into added development and manufacturing costs.
To design such complex IC chips, the IC chip development includes a design phase and a verification phase, of which the latter is critical to the determination of the workability and hence functionality of the chip, itself. For example, it is in the verification phase that a determination is made as to whether a design works as expected.
The verification phase has moved toward a software simulation approach to avoid the costs of first implementing designs in hardware to verify the workability of such designs. However, multiprocessor and multicore designs can lead to very large simulation models due to the fact that the entire design and testbench must be constructed for every simulation. Even when using modern simulation tools, simulation load and execution time, as well as build time can become cost and time prohibitive. This is especially true in complex design cases with inter-processor clusters since a complete gate level representation of the design must be constructed and loaded into the simulation for each processor.
By way of illustration, in verifying a design, a simulator (e.g., specialized software whose functions include accepting software written in a hardware description language (HDL) such as Verilog or VHDL) models a circuit design (e.g., a core) in order to simulate a response of the design. This response is applied by a test case to determine whether the design functions as expected. However, to achieve acceptably bug-free designs, the verification software must load the complete design into existing tools in order to satisfactorily verify the design, i.e., applying a number of test cases to fully exercise the design in simulation.
As the chip design becomes more complex in both individual cores and the interactions between cores, the verification tends to require an even more inordinate amount of time and computing resources, largely due to the modeling and verification of the interaction of functions associated with the entire design. That is, for example, the verification process becomes exponentially longer due to the need to load and exercise an entire test design for testing only one function or an interaction between two or more functions. This verification process becomes even more complicated for verification of multi-processor cores, which interact with one another, since no known technologies exist which can communicate with one another to verify the interactions between multi-processor cores. These inefficiencies in current verification methodologies exacerbate time pressures and increase, significantly, the time-to-market, a key factor for developers and marketers of IC chips in being competitive in business.